soc/intel: Remove blank lines before '}' and after '{'

Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

5 files changed, 0 insertions, 5 deletions

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index af7ee54188..f8d069e004 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -58,7 +58,6 @@ static const struct {
 };
 
 struct soc_intel_jasperlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 
diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c
index 3376aaa245..387fb591ce 100644
--- a/src/soc/intel/jasperlake/gpio.c
+++ b/src/soc/intel/jasperlake/gpio.c
@@ -32,7 +32,6 @@ static const struct reset_mapping rst_map_com0[] = {
  * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c
  */
 static const struct pad_group jsl_community0_groups[] = {
-
 	INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 320),		/* GPP_F */
 	INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),/* SPI0 */
 	INTEL_GPP_BASE(GPP_F0, GPP_B0, GPIO_GSPI1_CLK_LOOPBK, 32),/* GPP_B */
diff --git a/src/soc/intel/jasperlake/include/soc/meminit.h b/src/soc/intel/jasperlake/include/soc/meminit.h
index 5ba3e69db8..a8d3621657 100644
--- a/src/soc/intel/jasperlake/include/soc/meminit.h
+++ b/src/soc/intel/jasperlake/include/soc/meminit.h
@@ -52,7 +52,6 @@ struct spd_info {
 
 /* Board-specific memory dq mapping information */
 struct mb_cfg {
-
 	/*
 	 * For each channel, there are 6 sets of DQ byte mappings,
 	 * where each set has a package 0 and a package 1 value (package 0
diff --git a/src/soc/intel/jasperlake/meminit.c b/src/soc/intel/jasperlake/meminit.c
index 9cf5ecba67..9846160b1d 100644
--- a/src/soc/intel/jasperlake/meminit.c
+++ b/src/soc/intel/jasperlake/meminit.c
@@ -88,7 +88,6 @@ static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_c
 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 			const struct spd_info *spd_info, bool half_populated)
 {
-
 	if (spd_info->read_type == READ_SMBUS) {
 		for (int i = 0; i < NUM_DIMM_SLOT; i++)
 			mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];
diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c
index 3688f9e513..787eb77c91 100644
--- a/src/soc/intel/jasperlake/romstage/romstage.c
+++ b/src/soc/intel/jasperlake/romstage/romstage.c
@@ -139,7 +139,6 @@ void mainboard_romstage_entry(void)
 	fsp_memory_init(s3wake);
 	pmc_set_disb();
 	if (!s3wake) {
-
 		/*
 		 * cse_fw_sync() must be called after DRAM initialization as
 		 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())