diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-17 12:44:36 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-30 22:20:20 +0000 |
| commit | 82eaa21945539dfa533097dadfb91a1563304ff9 (patch) | |
| tree | b8d95266a7ab35fdd26c59420edf08b85434412d /src/soc/intel/jasperlake | |
| parent | 25d24523886f7f2feb5b017ea24f8900c4c603d4 (diff) | |
soc/intel/jasperlake: Send End-of-Post message to CSE
This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#619830.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55633
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake')
| -rw-r--r-- | src/soc/intel/jasperlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 10 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index b2c2dc4288..a05cd72a82 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -60,6 +60,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_SET_EOP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 0de02f28c6..5f33a3b055 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -23,9 +23,9 @@ * 2 - Send in DXE (Not applicable for FSP in API mode) */ enum { - EOP_DISABLE, - EOP_PEI, - EOP_DXE, + EOP_DISABLE = 0, + EOP_PEI = 1, + EOP_DXE = 2, } EndOfPost; static void parse_devicetree(FSP_S_CONFIG *params) @@ -81,8 +81,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->RtcMemoryLock = 1; } - /* Enable End of Post in PEI phase */ - params->EndOfPostMessage = EOP_PEI; + /* coreboot will send EOP before loading payload */ + params->EndOfPostMessage = EOP_DISABLE; /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); |