soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/intel/jasperlake/Makefile.mk b/src/soc/intel/jasperlake/Makefile.mk
index 31ea8657ee..1377fff9e0 100644
--- a/src/soc/intel/jasperlake/Makefile.mk
+++ b/src/soc/intel/jasperlake/Makefile.mk
@@ -22,6 +22,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -35,6 +36,7 @@ ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += systemagent.c