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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-06-15 13:04:48 +0300
committerAngel Pons <th3fanbus@gmail.com>2020-06-18 12:51:09 +0000
commit000d91af00af762b4ddc52f574a25e18c7aa1a0b (patch)
tree1d8109a70e7460f457489402f5aeb56f47d52aba /src/soc/intel/icelake/i2c.c
parent7ac76ecf9127d2b58467a49746b9fc112dd4ef4c (diff)
soc/intel,chromeos: Fix EC RO/RW status in GNVS
For baytrail and braswell, explicitly initialise it to ACTIVE_ECFW_RO without ChromeEC. For broadwell and skylake, fix it to report actual google_ec_running_ro() status. Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/i2c.c')
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