diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2024-09-17 15:06:50 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2024-09-19 09:07:32 +0000 |
| commit | 9c51ca52a447217c394717fde2bc97f64afd6781 (patch) | |
| tree | 7eebde8c73398157e06abb69c0f4471ec4edb495 /src/soc/intel/elkhartlake | |
| parent | 5d96f0d2e8c166d63e409ff4684cb445458f4c3e (diff) | |
soc/intel/ehl/fsp_params: Do not re-enable 'PchPwrOptEnable' for real-time tuning
If real-time tuning was enabled, 'PchPwrOptEnable' was set two times
with different values. This patch fixes the issue.
BUG=none
TEST=Enabled FSP UPD debug output and checked 'PchPwrOptEnable' offset
Change-Id: I2f31015c1da51a4ae1b8d5226f5d7b60a6023f3d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84399
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/elkhartlake')
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5e1bba78ea..90d1823f50 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -333,6 +333,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->D3ColdEnable = 0; params->PmcOsIdleEnable = 0; } else { + params->PchPwrOptEnable = 1; /* Enable PCH DMI Power Optimizer */ params->PchPostMasterClockGating = 1; params->PchPostMasterPowerGating = 1; } @@ -471,7 +472,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Custom1TurboActivationRatio = 0; params->Custom2TurboActivationRatio = 0; params->Custom3TurboActivationRatio = 0; - params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer params->TStates = 0x0; //Disable T state params->PkgCStateLimit = 0x7; //Set C state limit to C9 params->FastPkgCRampDisable[0] = 0x1; |