diff options
| author | Kapil Porwal <kapilporwal@google.com> | 2024-05-26 16:23:17 +0000 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-07 22:30:57 +0000 |
| commit | 83cd6f9f89eb473522a9a6536601acb64dd2863c (patch) | |
| tree | ab8f5e25210dab5e8ea9e0c328761f3cbd4b66c4 /src/soc/intel/common | |
| parent | 9a5cc9558616def2054d71f6ce82a7350b24e4b9 (diff) | |
soc/intel/cmn/cse: Support CSE sync from payload
Skip CSE sync in coreboot when payload is doing it.
BUG=b:305898363
TEST=Verify CSE sync from depthcharge on Screebo
Change-Id: Ifa942576c803b8ec9e1e59c61917a14154fb94b2
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/cse_lite.c | 6 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index b0524ea4f8..edc7e23d1b 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -150,6 +150,16 @@ config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD In this case, the HECI interface needs to stay visible and the payload must support sending commands to CSE. +config SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + bool + depends on SOC_INTEL_COMMON_BLOCK_CSE + help + Use this config to specify that the payload will update the CSE RW partition instead + of coreboot. + + In this case, CSE shall not switch to RW partition and the payload must support + CSE RW update. + config SOC_INTEL_CSE_LITE_SKU bool default n diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 3579bcea78..6e5b451c12 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -923,6 +923,9 @@ static bool is_cse_fw_update_enabled(void) if (!CONFIG(SOC_INTEL_CSE_RW_UPDATE)) return false; + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return false; + if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE)) return !is_debug_cse_fw_update_disable(); @@ -1499,6 +1502,9 @@ static void do_cse_fw_sync(void) void cse_fw_sync(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + timestamp_add_now(TS_CSE_FW_SYNC_START); do_cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); |