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| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-06-08 15:22:27 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-07-20 10:38:42 +0000 |
| commit | a9a92ac961f8f46b7cdca2176428d5e363f44912 (patch) | |
| tree | 88e0ee1c1fae6b186cda16b4ee476a72f98b90b9 /src/soc/intel/common | |
| parent | d31cbc74d1317aa5beb8619d93b9337d2c1370de (diff) | |
acpi: Move ECAM resource below PNP0C02 device in a common place
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.
As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index d605625bc5..44c873c8e5 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -269,11 +269,6 @@ Device (PDRC) */ Memory32Fixed (ReadWrite, 0, EP_BASE_SIZE, EGPB) - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - /* VTD engine memory range. */ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) @@ -301,12 +296,6 @@ Device (PDRC) CreateDwordField (BUF0, EGPB._BAS, EBR0) EBR0 = \_SB.PCI0.GEPB () - CreateDwordField (BUF0, PCIX._BAS, XBR0) - XBR0 = \_SB.PCI0.GPCB () - - CreateDwordField (BUF0, PCIX._LEN, XSZ0) - XSZ0 = \_SB.PCI0.GPCL () - CreateDwordField (BUF0, FIOH._BAS, FBR0) FBR0 = 0x100000000 - CONFIG_ROM_SIZE |