soc/intel/*: Use SSDT to pass A4GB and A4GS

GNVS is more fragile as you need to keep struct elements in sync with
ASL code.

Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

5 files changed, 29 insertions, 20 deletions

diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index bb7ab0c41c..2c72b7d2ac 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -22,7 +22,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	U2WE,	16,	// 0x2b - 0x2c USB2 Wake Enable Bitmap
 	U3WE,	16,	// 0x2d - 0x2e USB3 Wake Enable Bitmap
 	UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
-	A4GB,	64,	// 0x30 - 0x37 Base of above 4GB MMIO Resource
-	A4GS,	64,	// 0x38 - 0x3f Length of above 4GB MMIO Resource
-	,	64,	// 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
+	,	64,	// 0x30 - 0x37 Hest log buffer (used in SMM, not ASL code)
 }
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index be14d180bb..28d38edc0d 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -45,6 +45,9 @@ Device (MCHC)
 	}
 }
 
+External (A4GS, IntObj)
+External (A4GB, IntObj)
+
 Method (_CRS, 0, Serialized)
 {
 	Name (MCRS, ResourceTemplate ()
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 5adbdb8550..4fc5b4c4c8 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -24,9 +24,7 @@ struct __packed global_nvs {
 	u16	u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
 	u16	u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
 	u8	uior; /* 0x2f - UART debug controller init on S3 resume */
-	u64	a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
-	u64	a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
-	u64	hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */
+	u64	hest_log_addr; /* 0x30 - 0x37 err log addr (used in SMM, not ASL code) */
 };
 
 #endif
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index f708fae674..174c1a6d35 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -77,8 +77,6 @@ uintptr_t sa_get_gsm_base(void);
 uintptr_t sa_get_tseg_base(void);
 /* API to get TSEG size */
 size_t sa_get_tseg_size(void);
-/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(struct global_nvs *gnvs);
 /* API to lock PAM registers */
 void sa_lock_pam(void);
 
@@ -104,4 +102,7 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *base, uint64_t *mask);
 /* Returns the maximum supported capacity of a channel as encoded by DDRSZ in MiB */
 uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz);
 
+/* To be called in the acpi_fill_ssdt op of the domain */
+void ssdt_set_above_4g_pci(const struct device *dev);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_SA_H */
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 07bcb0cc73..51fb0e53da 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/cpu.h>
@@ -119,7 +120,7 @@ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = {
 };
 
 /* Read DRAM memory map register value through PCI configuration space */
-static void sa_read_map_entry(struct device *dev,
+static void sa_read_map_entry(const struct device *dev,
 		const struct sa_mem_map_descriptor *entry, uint64_t *result)
 {
 	uint64_t value = 0;
@@ -136,17 +137,6 @@ static void sa_read_map_entry(struct device *dev,
 	*result = value;
 }
 
-/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(struct global_nvs *gnvs)
-{
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-
-	sa_read_map_entry(sa_dev, &sa_memory_map[SA_TOUUD_REG], &gnvs->a4gb);
-	gnvs->a4gs = POWER_OF_2(cpu_phys_address_size()) - gnvs->a4gb;
-	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n",
-	       gnvs->a4gb, gnvs->a4gs);
-}
-
 static void sa_get_mem_map(struct device *dev, uint64_t *values)
 {
 	int i;
@@ -315,6 +305,25 @@ void sa_lock_pam(void)
 	pci_or_config8(dev, PAM0, PAM_LOCK);
 }
 
+void ssdt_set_above_4g_pci(const struct device *dev)
+{
+	if (dev->path.type != DEVICE_PATH_DOMAIN)
+		return;
+
+	uint64_t touud;
+	sa_read_map_entry(pcidev_path_on_root(SA_DEVFN_ROOT), &sa_memory_map[SA_TOUUD_REG],
+			  &touud);
+	const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
+
+	const char *scope = acpi_device_path(dev);
+	acpigen_write_scope(scope);
+	acpigen_write_name_qword("A4GB", touud);
+	acpigen_write_name_qword("A4GS", len);
+	acpigen_pop_len();
+
+	printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len);
+}
+
 static struct device_operations systemagent_ops = {
 	.read_resources   = systemagent_read_resources,
 	.set_resources    = pci_dev_set_resources,