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| author | Furquan Shaikh <furquan@google.com> | 2020-05-18 12:35:18 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-05-20 00:34:43 +0000 |
| commit | 5434deaf2a32e12c8b640fc80486b72d13408c01 (patch) | |
| tree | b011611700359d665960a5af6e128d77de300925 /src/soc/intel/common | |
| parent | eb72487784b19b77288dd7d589c0ffcc388dda33 (diff) | |
soc/intel/common/block/acpi: Fix error in shift operation for GPCL
CB:41454 updated northbridge.asl to ASL2.0 syntax. During this, GPCL
was incorrectly updated to use << (ShiftLeft) instead of >>
(ShiftRight). This change fixes the error in GPCL by updating it to
use >> (ShiftRight).
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for hatch.
Change-Id: I36469cb3b0bcc595acf0e43808d6a574986cad68
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/acpi/acpi/northbridge.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 53b21881ae..bac059076a 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -229,7 +229,7 @@ Method (GPCB, 0, Serialized) /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - Local0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Local0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ Return (Local0) } |