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authorArthur Heymans <arthur@aheymans.xyz>2018-01-29 16:34:46 +0100
committerArthur Heymans <arthur@aheymans.xyz>2018-02-06 22:40:06 +0000
commit742a0e911ca1682a06856731c69479aaf9c77ab4 (patch)
tree4535056ac7c4c0a502342b3d7bd5f3830fb2e678 /src/soc/intel/common/tpm_tis.c
parent3f7411e198a35f63cac575223c80668b37c4ac25 (diff)
nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESS
'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the use of fallback/normal with both the native raminit and the mrc.bin. Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that 128MB less is available to devices using the native raminit. Most devices reserve 2048M for non memory resources below 4G, which in most cases is more than adequate. Devices with only 1024M (and that don't already use the mrc.bin) are: * lenovo/x220 * lenovo/x230 * lenovo/x131e * lenovo/x1_carbon_gen1 Those could fail to allocate PCI resources, but on at least x220 with a somewhat default configuration (USB3 expresscard, Wireless PCIe card) it still boots fine, so one should not expect many problems from this change. Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/common/tpm_tis.c')
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