soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous

In case of CPU PCIe RPs, the RP numbers might not be contiguous for
all the functions in a slot.

Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as
per the FSP expectations.

Hence, this change updates the defintion of `struct pcie_rp_group` to
include a `start` member which indicates the starting PCI function
number within the group. All common functions for PCIe RP are
accordingly updated to take the `start` member into account.

Thus, in the above example, ADL can provide a cpu_rp_table as follows:
{
  { .slot = PCIE_SLOT_6, .start = 0, .count = 1 },
  { .slot = PCIE_SLOT_1, .start = 0, .count = 1 },
  { .slot = PCIE_SLOT_6, .start = 2, .count = 1 },
}

Since start defaults to 0 when uninitialized, current PCH RP group
tables don't need to be updated.

Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions