soc/intel/common/block: Add Intel common RTC code support

Create Intel Common RTC code. This code currently only
contains the code for configuring RTC required in Bootblock phase
which has the following programming -
* Enable upper 128 bytes of CMOS.

Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)

4 files changed, 57 insertions, 0 deletions

diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h
new file mode 100644
index 0000000000..1556026753
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/rtc.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_RTC_H
+#define SOC_INTEL_COMMON_BLOCK_RTC_H
+
+void enable_rtc_upper_bank(void);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_RTC_H */
diff --git a/src/soc/intel/common/block/rtc/Kconfig b/src/soc/intel/common/block/rtc/Kconfig
new file mode 100644
index 0000000000..d194f15d77
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_COMMON_BLOCK_RTC
+	bool
+	help
+	  Intel Processor common RTC support
diff --git a/src/soc/intel/common/block/rtc/Makefile.inc b/src/soc/intel/common/block/rtc/Makefile.inc
new file mode 100644
index 0000000000..2d2d4e3954
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/Makefile.inc
@@ -0,0 +1 @@
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c
diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c
new file mode 100644
index 0000000000..ea9987074b
--- /dev/null
+++ b/src/soc/intel/common/block/rtc/rtc.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/pcr_ids.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/rtc.h>
+
+/* RTC PCR configuration */
+#define PCR_RTC_CONF		0x3400
+#define PCR_RTC_CONF_UCMOS_EN	(1 << 2)
+#define PCR_RTC_CONF_LCMOS_LOCK	(1 << 3)
+#define PCR_RTC_CONF_UCMOS_LOCK	(1 << 4)
+#define PCR_RTC_CONF_RESERVED	(1 << 31)
+
+void enable_rtc_upper_bank(void)
+{
+	/* Enable upper 128 bytes of CMOS */
+	pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN);
+}