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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-23 10:52:01 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-24 10:02:06 +0000 |
| commit | 6da7fa26b021ecf36757c66869f49352bfdcacac (patch) | |
| tree | 6b84ffcb29975a50fcb4053b80a47877240e2ffe /src/soc/intel/common/block | |
| parent | cd96fed5dc3a203b076cbc74b337e59020d924ae (diff) | |
soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKE
Intel Apollolake does not support the bootguard MSRs 0x139 MSR_BC_PBEC
and 0x13A MSR_BOOT_GUARD_SACM_INFO.
Change-Id: Ief40028a1c85084e012a83db8080d478e407487b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram.S | 4 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 994c69750a..16844d94b6 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -107,3 +107,9 @@ config CPU_SUPPORTS_PM_TIMER_EMULATION Select this if the SoC's ucode supports PM ACPI timer emulation (Common timer Copy), which is required to be able to disable the TCO PM ACPI timer for power saving. + +config SOC_INTEL_NO_BOOTGUARD_MSR + bool + help + Select this on platforms that do not support Bootguard related MSRs + 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d880c2588d..29bd3fe87f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -66,9 +66,13 @@ * Returns %eax and sets/unsets zero flag */ .macro is_bootguard_nem +#if CONFIG(SOC_INTEL_NO_BOOTGUARD_MSR) + xorl %eax, %eax +#else movl $MSR_BOOT_GUARD_SACM_INFO, %ecx rdmsr andl $B_BOOT_GUARD_SACM_INFO_NEM_ENABLED, %eax +#endif .endm .global bootblock_pre_c_entry |