diff options
| author | Furquan Shaikh <furquan@google.com> | 2021-10-09 00:08:56 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-10-19 16:09:49 +0000 |
| commit | 3f0d64329cbf7c37ace03c98113f76e3862b11e4 (patch) | |
| tree | e0b54471ca7f819b3b5c29ce17f44273cb90530f /src/soc/intel/common/block | |
| parent | 0a0182e13d2124de3328a90b4a4d556f60d3bf8f (diff) | |
soc/intel/common/cse: Support RW update when stitching CSE binary
This change updates the STITCH_ME_BIN path to enable support for
including CSE RW update in CBFS. CSE_RW_FILE is set to either
CONFIG_SOC_INTEL_CSE_RW_FILE or CSE_BP2_BIN depending upon the
selection of STITCH_ME_BIN config.
BUG=b:189177580
Change-Id: I0478f6b2a3342ed29c7ca21aa8e26655c58265f4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/common/block')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/Makefile.inc | 12 |
2 files changed, 9 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4305deaf2b..d1f4d33342 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -64,7 +64,7 @@ config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME CBFS name for Intel CSE CBFS RW version file config SOC_INTEL_CSE_RW_FILE - string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE + string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN default "" help Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 5c81d892f8..13f879ef9f 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -11,6 +11,7 @@ ifeq ($(CONFIG_STITCH_ME_BIN),y) CSE_BP1_BIN := $(objcse)/cse_bp1.bin CSE_BP2_BIN := $(objcse)/cse_bp2.bin CSE_LAYOUT_BIN := $(objcse)/cse_layout.bin +CSE_RW_FILE := $(CSE_BP2_BIN) CSE_BPDT_VERSION := $(call strip_quotes,$(CONFIG_CSE_BPDT_VERSION)) ifeq ($(CONFIG_CSE_BPDT_VERSION),) @@ -70,16 +71,19 @@ endif ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) +ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") +$(error "CSE RW version is missing and need to be set by mainboard config") +endif + +ifneq ($(CONFIG_STITCH_ME_BIN),y) + ifeq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") $(error "CSE RW file path is missing and need to be set by mainboard config") endif +CSE_RW_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -ifeq ($(CONFIG_SOC_INTEL_CSE_RW_VERSION),"") -$(error "CSE RW version is missing and need to be set by mainboard config") endif -CSE_RW_FILE=$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) - CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) regions-for-file-$(CSE_LITE_ME_RW) = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME)), \ $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME)) |