diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2023-07-06 16:05:42 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-18 05:31:15 +0000 |
| commit | fa77ac93c5b63ab56135436cc34d97ab60b57470 (patch) | |
| tree | 85ecdb7aa1328012963e5b14b02bad006d7e886b /src/soc/intel/common/block/pcie/Kconfig | |
| parent | fadda4ae6b1614523e14326fbe98280ff0c19c64 (diff) | |
soc/intel/common/acpi: Support on/off PCIe CLK by P2SB
In the older platform such as Raptor Lake (RPL), Tiger Lake (TGL), it
needs PMC IPC cmd to turn on/off the corresponding clock.
Now on Meteor Lake (MTL), it control pcie clock registers on P2SB on
IOE or SoC die.
BUG=b:288976547, b:289461604
TEST=Test on google/screebo and found the pcie clock is on/off properly
and sdcard pcie port doesn't block S0ix with RTD3 cold enabled.
Change-Id: Ia729444b561daafc2dca0ed86c797eb98ce1f165
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76347
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/pcie/Kconfig')
| -rw-r--r-- | src/soc/intel/common/block/pcie/Kconfig | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index f65d8c16f3..dccedb0df4 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -37,3 +37,19 @@ config PCIE_DEBUG_INFO Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits. + +config PCIE_CLOCK_CONTROL_THROUGH_P2SB + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + help + Enables PCIe CLK control (on/off) through P2SB. The mechanism is supported + starting from MTL platform. In older platforms like ADL & TGL, PCIe CLK is + controlled by sending IPC CMD to PMC. + +config IOE_DIE_CLOCK_START + int + depends on SOC_INTEL_COMMON_BLOCK_IOE_P2SB + default 0 + help + The beginning of IOE DIE pcie src clk number. IOE DIE is started from MTL. |