diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2023-03-12 12:24:58 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-04 08:07:56 +0000 |
| commit | 94050499ca9fa1b1ebb7a867eea3f722a4ca85c9 (patch) | |
| tree | d90306b162dcf5e1cd50203fd139643190529b6e /src/soc/intel/common/block/cse | |
| parent | fb1b192cf1c101dad40991081e406dddf52bd7fd (diff) | |
soc/intel/alderlake: Add support for CSE timestamp data versions
CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.
BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/Kconfig | 14 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cse/telemetry.c | 18 |
2 files changed, 18 insertions, 14 deletions
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55c9e7999e..33d703fb50 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -211,6 +211,20 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 1 of the CSE timestamp + definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). + +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 2 of the CSE timestamp + definitions, it can be used for Meteor Lake M/P. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default y diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 5f36360574..6502be99c9 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -6,11 +6,11 @@ #define MSEC_TO_USEC(x) (x * 1000) -static void cbmem_inject_telemetry_data(void) +static void process_cse_telemetry_data(void) { struct cse_boot_perf_rsp cse_perf_data; s64 ts[NUM_CSE_BOOT_PERF_DATA] = {0}; - s64 current_time, start_stamp; + s64 current_time; int zero_point_idx = 0; /* @@ -60,17 +60,7 @@ static void cbmem_inject_telemetry_data(void) } /* Inject CSME timestamps into the coreboot timestamp table */ - start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; - - timestamp_add(TS_ME_ROM_START, start_stamp); - timestamp_add(TS_ME_BOOT_STALL_END, - start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); - timestamp_add(TS_ME_ICC_CONFIG_START, - start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); - timestamp_add(TS_ME_HOST_BOOT_PREP_END, - start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); - timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, - start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + soc_cbmem_inject_telemetry_data(ts, current_time); } void cse_get_telemetry_data(void) @@ -81,5 +71,5 @@ void cse_get_telemetry_data(void) return; } - cbmem_inject_telemetry_data(); + process_cse_telemetry_data(); } |