diff options
| author | Martin Roth <gaumless@gmail.com> | 2022-11-20 17:56:44 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-23 03:48:32 +0000 |
| commit | 8c974509ea90eec18e22027c3e71de3e875fc964 (patch) | |
| tree | 63e4a193eaedede47dab4fd50c234fbfd79312f4 /src/soc/intel/common/block/cse | |
| parent | d05ea79e40c4a7c6e19a3804ad14eaa4ece38402 (diff) | |
soc/intel/common: Define post codes
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/block/cse')
| -rw-r--r-- | src/soc/intel/common/block/cse/cse.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index ceb75e2984..c2d44846ff 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> +#include <intelblocks/post_codes.h> #include <option.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -611,7 +612,7 @@ int heci_reset(void) uint32_t csr; /* Clear post code to prevent eventlog entry from unknown code. */ - post_code(0); + post_code(POST_CODE_ZERO); /* Send reset request */ csr = read_host_csr(); |