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author | Felix Held <felix-coreboot@felixheld.de> | 2024-08-24 14:18:19 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-27 11:35:36 +0000 |
commit | 9c8debf6b53c451559f4372ab9c7682b860f8fd6 (patch) | |
tree | fdbf7d3e1672e88057c04b8b2b82a7fae28199d1 /src/soc/intel/cannonlake/xhci.c | |
parent | 975b061e346e830ef14ce9a39e62260bce24a8b6 (diff) |
soc/amd/stoneyridge/smihandler: add PSP SMI handler
Now that the PSP SMI handler for flash access is also implemented for
the PSP generation 1, the PSP SMI handler can be added to the
Stoneyridge code too. The actual PSP SMI handler code will only be added
to the build when SOC_AMD_COMMON_BLOCK_PSP_SMI is selected which isn't
the default case, so this patch doesn't change the current behavior
unless that option is also selected. This SMI handler mainly added for
completeness since the PSP firmware blobs released for Stoneyridge are
probably lacking the corresponding PSP-side code to send the PSP SMI to
the host. At least if I remember correctly the PSP bootloader release
for Stoneyridge has the ability to load the secure OS removed and since
the secure OS is the runtime component, some part of that is probably
what's sending those SMIs to the host. If there are some other PSP
bootloader builds that support loading the secure OS, this patch might
still be useful for those.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78944e2de86bc1e8e277d22a7a8da517622f49a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84077
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/xhci.c')
0 files changed, 0 insertions, 0 deletions