diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2019-07-03 13:02:37 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-19 17:13:50 +0000 |
| commit | 0f718312f1b57ec300b7486c95e53562be5a2325 (patch) | |
| tree | a9a224c621433a8e6af62c4d31f73011d263c145 /src/soc/intel/cannonlake/elog.c | |
| parent | a260215a644f0f13b60c08b1a9d55d3567a380b1 (diff) | |
soc/intel/common: Add SOC specific function to get XHCI USB info
It feels appropriate to define SoC specific XHCI USB info in SoC
specific XHCI source file and an API to get that information instead of
defining it in elog source file. This will help in other situations
where the information is required.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/elog.c')
| -rw-r--r-- | src/soc/intel/cannonlake/elog.c | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 141aa45b02..0bccdb7880 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -24,18 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> -#define XHCI_USB2_PORT_STATUS_REG 0x480 -#define XHCI_USB3_PORT_STATUS_REG 0x580 -#define XHCI_USB2_PORT_NUM 14 -#define XHCI_USB3_PORT_NUM 10 - -static const struct xhci_usb_info usb_info = { - .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, - .num_usb2_ports = XHCI_USB2_PORT_NUM, - .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, - .num_usb3_ports = XHCI_USB3_PORT_NUM, -}; - static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -68,7 +56,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(&usb_info); + pch_xhci_update_wake_event(soc_get_xhci_usb_info()); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) |