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| author | Elyes Haouas <ehaouas@noos.fr> | 2024-07-19 11:59:50 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-08-28 00:35:27 +0000 |
| commit | 8c4d7e7e9112d079687a1679799c659b576e96cb (patch) | |
| tree | bf591eb03470ed8b79ea9a524827ecdf64344c9b /src/soc/intel/cannonlake/chip.h | |
| parent | 9c8debf6b53c451559f4372ab9c7682b860f8fd6 (diff) | |
tree: Use boolean for "eist_enable"
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 1e7e5a5225..97657e2feb 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,7 +237,7 @@ struct soc_intel_cannonlake_config { /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ + /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ |