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authorElyes Haouas <ehaouas@noos.fr>2024-08-31 07:29:00 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-09-04 01:16:40 +0000
commit2f8b77b76bdbb6e93f1a9ca3c73f9bb38ec55b41 (patch)
tree862af999e15ccf9df92701e3d007e2e902132ba7 /src/soc/intel/cannonlake/chip.h
parent37c85f0cf54c992d283b5f306ce43b9522c515f2 (diff)
tree: Drop unnecessary "true/false" comments
Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
-rw-r--r--src/soc/intel/cannonlake/chip.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 97657e2feb..9459b88808 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -237,10 +237,7 @@ struct soc_intel_cannonlake_config {
/* Enables support for Teton Glacier hybrid storage device */
bool TetonGlacierMode;
- /* Enable/Disable EIST. true:Enabled, false:Disabled */
bool eist_enable;
-
- /* Enable C6 DRAM */
bool enable_c6dram;
/*