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authorKilari Raasi <kilari.raasi@intel.com>2023-11-07 14:05:14 +0530
committerSubrata Banik <subratabanik@google.com>2023-12-11 05:06:18 +0000
commitebb28c523ef154beee3e9afdc6262df7ce28e03c (patch)
tree24117bbce13331ada1476d3b5251df7973dab9a9 /src/soc/intel/cannonlake/Makefile.inc
parentb21bc9d9dffd84886081462cd0555f201e023f4b (diff)
soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs
By default MarginLimitCheck and RMC UPDs are enabled in FSP which enables fast and cold boot retraining causing the boot time increase. So, disabling the same UPDs to fix it. Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
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