coreboot: common stage cache

Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.

Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

4 files changed, 20 insertions, 61 deletions

diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index 6dec3b9158..201825a93b 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -25,7 +25,7 @@
 #include <cpu/x86/tsc.h>
 #include <program_loading.h>
 #include <rmodule.h>
-#include <ramstage_cache.h>
+#include <stage_cache.h>
 #include <string.h>
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/vboot_handoff.h>
@@ -34,67 +34,20 @@
 #include <soc/pei_wrapper.h>
 #include <soc/ramstage.h>
 
-static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
-{
-	return (struct ramstage_cache *)&c->program[c->size];
-}
-
 static pei_wrapper_entry_t load_refcode_from_cache(void)
 {
-	struct ramstage_cache *c;
-	long cache_size;
+	struct prog refcode;
 
 	printk(BIOS_DEBUG, "refcode loading from cache.\n");
 
-	c = ramstage_cache_location(&cache_size);
-
-	if (!ramstage_cache_is_valid(c)) {
-		printk(BIOS_DEBUG, "Invalid ramstage cache descriptor.\n");
-		return NULL;
-	}
+	stage_cache_load_stage(STAGE_REFCODE, &refcode);
 
-	c = next_cache(c);
-	if (!ramstage_cache_is_valid(c)) {
-		printk(BIOS_DEBUG, "Invalid refcode cache descriptor.\n");
-		return NULL;
-	}
-
-	printk(BIOS_DEBUG, "Loading cached reference code from 0x%08x(%x)\n",
-	       c->load_address, c->size);
-	memcpy((void *)c->load_address, &c->program[0], c->size);
-
-	return (pei_wrapper_entry_t)c->entry_point;
+	return (pei_wrapper_entry_t)prog_entry(&refcode);
 }
 
 static void cache_refcode(const struct rmod_stage_load *rsl)
 {
-	struct ramstage_cache *c;
-	long cache_size;
-
-	c = ramstage_cache_location(&cache_size);
-
-	if (!ramstage_cache_is_valid(c)) {
-		printk(BIOS_DEBUG, "No place to cache reference code.\n");
-		return;
-	}
-
-	/* Determine how much remaining cache available. */
-	cache_size -= c->size + sizeof(*c);
-
-	if (cache_size < (sizeof(*c) + prog_size(rsl->prog))) {
-		printk(BIOS_DEBUG, "Not enough cache space for ref code.\n");
-		return;
-	}
-
-	c = next_cache(c);
-	c->magic = RAMSTAGE_CACHE_MAGIC;
-	c->entry_point = (uint32_t)(uintptr_t)prog_entry(rsl->prog);
-	c->load_address = (uint32_t)(uintptr_t)prog_start(rsl->prog);
-	c->size = prog_size(rsl->prog);
-
-	printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n",
-	       &c->program[0], c->size);
-	memcpy(&c->program[0], (void *)c->load_address, c->size);
+	stage_cache_add(STAGE_REFCODE, rsl->prog);
 }
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 1f62fd0c8c..52ea49100d 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -29,6 +29,7 @@
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 #endif
+#include <stage_cache.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/intel/common/mrc_cache.h>
 #include <soc/iomap.h>
@@ -111,12 +112,16 @@ void raminit(struct pei_data *pei_data)
 
 	if (pei_data->boot_mode != SLEEP_STATE_S3) {
 		cbmem_initialize_empty();
-	} else if (cbmem_initialize()) {
+		stage_cache_create_empty();
+	} else {
+		stage_cache_recover();
+		if (cbmem_initialize()) {
 #if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
-		/* Failed S3 resume, reset to come up cleanly */
-		reset_system();
+			printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+			/* Failed S3 resume, reset to come up cleanly */
+			reset_system();
 #endif
+		}
 	}
 
 	printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index bf9e2ed3e9..1741ae6b82 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -25,11 +25,12 @@
 #include <arch/stages.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
+#include <cbfs.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>
-#include <ramstage_cache.h>
 #include <romstage_handoff.h>
+#include <stage_cache.h>
 #include <timestamp.h>
 #include <soc/me.h>
 #include <soc/pei_data.h>
@@ -142,7 +143,7 @@ void asmlinkage romstage_after_car(void)
 	while (1);
 }
 
-void ramstage_cache_invalid(struct ramstage_cache *cache)
+void ramstage_cache_invalid(void)
 {
 #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
 	/* Perform cold reset on invalid ramstage cache. */
diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c
index cb34297cdd..346e673cf5 100644
--- a/src/soc/intel/broadwell/stage_cache.c
+++ b/src/soc/intel/broadwell/stage_cache.c
@@ -18,11 +18,11 @@
  */
 
 #include <cbmem.h>
-#include <ramstage_cache.h>
 #include <soc/smm.h>
+#include <stage_cache.h>
 #include <stdint.h>
 
-struct ramstage_cache *ramstage_cache_location(long *size)
+void stage_cache_external_region(void **base, size_t *size)
 {
 	/* The ramstage cache lives in the TSEG region.
 	 * The top of ram is defined to be the TSEG base address. */
@@ -30,6 +30,6 @@ struct ramstage_cache *ramstage_cache_location(long *size)
 	offset -= CONFIG_IED_REGION_SIZE;
 	offset -= CONFIG_SMM_RESERVED_SIZE;
 
+	*base = (void *)(cbmem_top() + offset);
 	*size = CONFIG_SMM_RESERVED_SIZE;
-	return (void *)(cbmem_top() + offset);
 }