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authorKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-08 09:43:56 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-26 11:03:13 +0000
commit81dc352032cacb309ed9335f394969d847820511 (patch)
treeaab56a7a8917ccab831a6eb7400ffa6b645bf323 /src/soc/intel/broadwell/pch/Kconfig
parent7f8e2a6a4a9cb1544ef8fa19850abeb3d4213931 (diff)
intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC
Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/broadwell/pch/Kconfig')
-rw-r--r--src/soc/intel/broadwell/pch/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig
index 63f0439e6a..bd1bea5f20 100644
--- a/src/soc/intel/broadwell/pch/Kconfig
+++ b/src/soc/intel/broadwell/pch/Kconfig
@@ -4,6 +4,7 @@ config INTEL_LYNXPOINT_LP
config PCH_SPECIFIC_OPTIONS
def_bool y
+ select ACPI_COMMON_MADT_IOAPIC
select ACPI_COMMON_MADT_LAPIC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_SOC_NVS
@@ -17,7 +18,6 @@ config PCH_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_LYNXPOINT_LP
select RTC
- select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_RTC