diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-01 08:20:17 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 20:56:54 +0000 |
| commit | 2eb100dd123e6f73e41f5c3c270c9e2f4c334ba7 (patch) | |
| tree | 91de347ba31b9047e1bc0805b4490ec9ed80b454 /src/soc/intel/braswell/tsc_freq.c | |
| parent | 593941b600623ed366ada5ee8bb0dc94318b7b02 (diff) | |
soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM
method. This allows the ACPI tables to expose device/IP power states
requirements for different system low power states
BUG=b:185437326
TEST=Along with following patch on brya0 after resume from s0ix,
cat /sys/kernel/debug/pmc_core/substate_requirements
Element | S0i2.0 | S0i3.0 | Status |
USB2PLL_OFF_STS | Required | Required | Yes |
PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | Yes |
PCIe_Gen3PLL_OFF_STS | Required | Required | Yes |
OPIOPLL_OFF_STS | Required | Required | Yes |
OCPLL_OFF_STS | Required | Required | Yes |
MainPLL_OFF_STS | | Required | |
MIPIPLL_OFF_STS | Required | Required | Yes |
Fast_XTAL_Osc_OFF_STS | | Required | |
AC_Ring_Osc_OFF_STS | Required | Required | Yes |
SATAPLL_OFF_STS | Required | Required | Yes |
XTAL_USB2PLL_OFF_STS | | Required | Yes |
CSME_PG_STS | Required | Required | Yes |
SATA_PG_STS | Required | Required | Yes |
xHCI_PG_STS | Required | Required | Yes |
UFSX2_PG_STS | Required | Required | Yes |
OTG_PG_STS | Required | Required | Yes |
SPA_PG_STS | Required | Required | Yes |
SPB_PG_STS | Required | Required | Yes |
SPC_PG_STS | Required | Required | Yes |
THC0_PG_STS | Required | Required | Yes |
THC1_PG_STS | Required | Required | Yes |
GBETSN_PG_STS | Required | Required | Yes |
GBE_PG_STS | Required | Required | Yes |
LPSS_PG_STS | Required | Required | Yes |
ADSP_D3_STS | | Required | Yes |
xHCI0_D3_STS | Required | Required | Yes |
xDCI1_D3_STS | Required | Required | Yes |
IS_D3_STS | Required | Required | Yes |
GBE_TSN_D3_STS | Required | Required | Yes |
CPU_C10_REQ_STS_0 | Required | Required | Yes |
CNVI_REQ_STS_6 | | Required | Yes |
ISH_REQ_STS_7 | | Required | Yes |
MPHY_Core_DL_REQ_STS_16 | Required | Required | Yes |
Break-even_En_REQ_STS_17 | Required | Required | Yes |
Auto-demo_En_REQ_STS_18 | Required | Required | Yes |
Int_Timer_SS_Wake0_Pol_STS | Required | Required | |
Int_Timer_SS_Wake1_Pol_STS | Required | Required | |
Int_Timer_SS_Wake2_Pol_STS | Required | Required | |
Int_Timer_SS_Wake3_Pol_STS | Required | Required | |
Int_Timer_SS_Wake4_Pol_STS | Required | Required | |
Int_Timer_SS_Wake5_Pol_STS | Required | Required | |
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56005
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/braswell/tsc_freq.c')
0 files changed, 0 insertions, 0 deletions