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| author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2020-12-30 17:38:06 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-07 08:12:43 +0000 |
| commit | ed47332ff6511874191e5d1e95f2e6f3d01e5a35 (patch) | |
| tree | aa061b35d56769a998703c5a0ca7d9200b002bca /src/soc/intel/braswell/pcie.c | |
| parent | cd6998b810c68464c5fa28d60c9d0f8fe80679eb (diff) | |
mb/google/dedede/var/metaknight: Configure I2C high and low times
Configure the I2C bus high and low times for port0,2 and 4 I2C buses.
BUG=b:176519792
TEST=Measured the I2C bus frequency lower than 400 KHz.
Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/braswell/pcie.c')
0 files changed, 0 insertions, 0 deletions