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authorMatt DeVillier <matt.devillier@gmail.com>2023-10-27 15:18:22 -0500
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-11-03 15:33:50 +0000
commit4f961371a5d48335e64623ee0840840b34fd25c3 (patch)
treead6e55e50fc046d279423cc4af147ea30ddfdd7f /src/soc/intel/braswell/Kconfig
parent96a7d9e76bb8fc008fb907c6234f0aee294d32f7 (diff)
soc/intel/braswell: Unify DPTF enablement
Currently, there are 3 separate settings for DPTF which are not always in sync: - the enabled/disabled state of the devicetree PCI device - the 'dptf_enable' register, which sets the ACPI device status via GNVS - the 'DptfDisable' register, which sets the FSP UPD of the same name To make things sane, drop the two chip registers, and set the GNVS variable and FSP UPD based on the enabled/disabled status of the DPTF PCI device in the mainboard's devicetree. TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI devices are present/enabled when DPTF is enabled in devicetree, and not present/disabled when disabled in devicetree. Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
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