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author | Duncan Laurie <dlaurie@google.com> | 2020-10-10 00:15:28 +0000 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2020-11-20 00:24:11 +0000 |
commit | 64bc26ad1553eec6bbbd6deac21a3e79ca7ce455 (patch) | |
tree | 3b8b66a3b3abfbe6e0f26f8d37ea85c44943b24f /src/soc/intel/baytrail/modphy_table.c | |
parent | 05c732b9e4c6cac921416d26e9e4febdc63d5772 (diff) |
soc/intel/common: Add PCIe Runtime D3 driver for ACPI
This driver is for devices attached to a PCIe root port that support
Runtime D3. It creates the necessary PowerResource in the root port to
provide _ON/_OFF methods for which will turn off power and clocks to the
device when it is in the D3cold state.
The mainboard declares the driver in devicetree and provides the GPIOs
that control power/reset for the device attached to the root port and
the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock.
An additional device property is created for storage devices if it
matches the PCI storage class which is used to indicate that the storage
device should use D3 for power savings.
BUG=b:160996445
TEST=boot on volteer device with this driver enabled in the devicetree
and disassemble the SSDT to ensure this code exists.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/baytrail/modphy_table.c')
0 files changed, 0 insertions, 0 deletions