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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-06-15 14:32:46 +0200
committerJakub Czapiga <jacz@semihalf.com>2023-06-19 11:09:47 +0000
commit8c822189bd94527eb2e622ff31576a316bb6e35e (patch)
tree6837a95fdcccdf1d794e4e5869413ec7ae82c269 /src/soc/intel/apollolake
parent16d1eb68d2e8c72a9ce1bca59cde21cd58452e66 (diff)
soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump
For a unification of the naming convension, change from pascal case to snake case style for parameter 'ModPhyVoltageBump'. Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/apollolake')
-rw-r--r--src/soc/intel/apollolake/chip.c2
-rw-r--r--src/soc/intel/apollolake/chip.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index a29ba3b19f..956a55b4a7 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -617,7 +617,7 @@ static void glk_fsp_silicon_init_params_cb(
/*
* Options to bump USB3 LDO voltage with 40mv.
*/
- silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump;
+ silconfig->ModPhyVoltageBump = cfg->mod_phy_voltage_bump;
/*
* Options to adjust PMIC Vdd2 voltage.
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 26e4478da2..5a3aa880c5 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -196,7 +196,7 @@ struct soc_intel_apollolake_config {
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.
* 0:FALSE (default), 1:True.
*/
- uint8_t ModPhyVoltageBump;
+ uint8_t mod_phy_voltage_bump;
/* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
* the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage