diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-02-08 01:01:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-02-12 04:13:23 +0000 |
| commit | e9fd562a833f9a5754cd2398444f519d1fd410c6 (patch) | |
| tree | 75ec3bbd32effd8190bc980fd9262d9417c97fd3 /src/soc/intel/alderlake | |
| parent | a2eca49d837880dbdb8f07c7022fc740def4e4e4 (diff) | |
soc/intel/cmn/sa: Refactor SA common code
Leverages common SA header definitions for Host Bridge registers.
Renames DSM_BASE_ADDR_REG to BDSM and DPR_REG to DPR for brevity.
Additionally, made some minor code alignment corrections while
adding newer macros in the header file.
TEST= Build and boot successful on google/screebo.
Change-Id: I476f213d75a0978336b3749a5ba1499107eb2238
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/systemagent.h | 19 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 4 |
2 files changed, 10 insertions, 13 deletions
diff --git a/src/soc/intel/alderlake/include/soc/systemagent.h b/src/soc/intel/alderlake/include/soc/systemagent.h index 36d339884b..b7a2957c18 100644 --- a/src/soc/intel/alderlake/include/soc/systemagent.h +++ b/src/soc/intel/alderlake/include/soc/systemagent.h @@ -64,17 +64,14 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = { #define LT_SECURITY_SIZE (128 * KiB) #define APIC_SIZE (1 * MiB) -#define MASK_PCIEXBAR_LENGTH 0x0000000E // bits [3:1] -#define PCIEXBAR_LENGTH_LSB 1 // used to shift right - -#define DSM_BASE_ADDR_REG 0xB0 -#define MASK_DSM_LENGTH 0xFF00 // [15:8] -#define MASK_DSM_LENGTH_LSB 8 // used to shift right -#define MASK_GSM_LENGTH 0xC0 // [7:6] -#define MASK_GSM_LENGTH_LSB 6 // used to shift right -#define DPR_REG 0x5C -#define MASK_DPR_LENGTH 0xFF0 // [11:4] -#define MASK_DPR_LENGTH_LSB 4 // used to shift right +#define MASK_PCIEXBAR_LENGTH 0xE /* bits [3:1] */ +#define PCIEXBAR_LENGTH_LSB 1 /* used to shift right */ +#define MASK_DSM_LENGTH 0xFF00 /* bits [15:8] */ +#define MASK_DSM_LENGTH_LSB 8 /* used to shift right */ +#define MASK_GSM_LENGTH 0xC0 /* bits [7:6] */ +#define MASK_GSM_LENGTH_LSB 6 /* used to shift right */ +#define MASK_DPR_LENGTH 0xFF0 /* bits [11:4] */ +#define MASK_DPR_LENGTH_LSB 4 /* used to shift right */ uint64_t get_mmcfg_size(const struct device *dev); uint64_t get_dsm_size(const struct device *dev); diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 36fa45b9e5..ecd704e569 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -111,7 +111,7 @@ void soc_add_configurable_mmio_resources(struct device *dev, int *resource_cnt) /* DSM */ size = get_dsm_size(dev); if (size > 0) { - base = pci_read_config32(dev, DSM_BASE_ADDR_REG) & 0xFFF00000; + base = pci_read_config32(dev, BDSM) & 0xFFF00000; set_mmio_resource(&(cfg_rsrc[count++]), base, size, "DSM"); } @@ -316,7 +316,7 @@ uint64_t get_gsm_size(const struct device *dev) uint64_t get_dpr_size(const struct device *dev) { uint64_t size; - uint32_t dpr_reg = pci_read_config32(dev, DPR_REG); + uint32_t dpr_reg = pci_read_config32(dev, DPR); uint32_t size_field = (dpr_reg & MASK_DPR_LENGTH) >> MASK_DPR_LENGTH_LSB; size = (uint64_t)size_field * MiB; return size; |