diff options
| author | Scott Chao <scott_chao@wistron.corp-partner.google.com> | 2022-04-20 15:16:06 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-27 12:28:17 +0000 |
| commit | ab638c17e2178308e6aa497edcee8067ac798730 (patch) | |
| tree | f21106f3bfcb6ceb0b86c857a764133e6ec359a4 /src/soc/intel/alderlake | |
| parent | 0ed3dfc92aac24eeca26081c4ac49c3df9d5907b (diff) | |
soc/intel/adl/chip.h: Rename max_dram_speed to include units
The unit of dram speed is MT/s so append it on variable name.
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 8ee36f63bc..7934a8635a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -484,7 +484,7 @@ struct soc_intel_alderlake_config { */ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; - uint16_t max_dram_speed; + uint16_t max_dram_speed_mts; enum { SLP_S3_ASSERTION_DEFAULT, diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 83ce074506..863fc43ffa 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -141,8 +141,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, { m_cfg->SaGv = config->sagv; m_cfg->RMT = config->RMT; - if (config->max_dram_speed) - m_cfg->DdrFreqLimit = config->max_dram_speed; + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |