diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-11-17 15:26:24 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-11-20 05:18:08 +0000 |
| commit | 5a13d6617cde9c676ce72b31c79a272c70449d29 (patch) | |
| tree | 0b28e4e5e414946978d5bc7464092601a750550e /src/soc/intel/alderlake | |
| parent | ca247629da034e252d2645c7f15a821b0333454f (diff) | |
soc/intel/common/thermal: Use `clrsetbits32()` for setting LTT
This patch uses `clrsetbits32` helper function to set thermal
device Low Temp Threshold (LTT) value.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp with this change.
Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake')
0 files changed, 0 insertions, 0 deletions