diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2021-02-22 15:13:05 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-24 11:28:45 +0000 |
| commit | 4742f537705e1b3a97dd737bb8a1fc13fc89f7f7 (patch) | |
| tree | 0cd4da3fff6cc92cd9d8ee92bfdcca1ca14ea17f /src/soc/intel/alderlake | |
| parent | a04d37ccb3263994d28db6c586cf51611f139ba1 (diff) | |
soc/intel/{adl,jsl,ehl,tgl}: Remove ITSS polarity restore
Post boot SAI PCR access to ITSS polarity regsiter is locked.
Restore of ITSS polarity does not take effect anyways. Hence
removing the related programming.
Change-Id: I1adab45ee903b9d9c1d98a060143445c0cee0968
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 95ad8657ab..977705268b 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -127,20 +127,12 @@ static void soc_fill_gpio_pm_configuration(void) void soc_init_pre_device(void *chip_info) { - /* TODO: A bug has been filed, remove this W/A once FSP is updated */ - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - soc_fill_gpio_pm_configuration(); /* Swap enabled PCI ports in device tree if needed. */ |