diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-05-03 22:24:15 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-04 15:03:44 +0000 |
| commit | 633e0f2264cb58f4575d2b2f8868b628d939ed70 (patch) | |
| tree | 10545bb8f7ab9bb57f548521b94b66cf19917d74 /src/soc/intel/alderlake | |
| parent | 808c95056604bf4c33cb5f1246273604d83b7069 (diff) | |
soc/intel/alderlake: remove duplicate PL2 override
PL2 override value is already declared under common code in power_limit.h file.
Removing this duplicate PL2 override from soc specific header file.
BRANCH=None
BUG=None
TEST=Built and tested on brya
Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 201150e8fc..fb9dd73730 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -162,8 +162,6 @@ struct soc_intel_alderlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; |