diff options
| author | Kane Chen <kane.chen@intel.corp-partner.google.com> | 2023-05-08 14:25:10 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-07-18 19:07:32 +0000 |
| commit | caa8a20d87646ab46b49d985b55175227129fdc8 (patch) | |
| tree | ec0baa8e7b2565bf3e06eeb885fbcbadfcb8cb13 /src/soc/intel/alderlake/include | |
| parent | ea025af4dcf7f7642cda61a05089b140c39670b6 (diff) | |
soc/intel/alderlake: Hook up CsPiStartHighinEct UPD
This commit provides option for board to set CsPiStartHighinEct
FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field.
BUG=b:279835630
BRANCH=none
TEST=CsPiStartHighinEct UPD is set properly
Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/meminit.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index bd75636e9b..1d9eaf9414 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -107,6 +107,10 @@ struct mb_cfg { /* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */ uint8_t LpDdrDqDqsReTraining; + + /* Enable/Disable Cs Pi Start with High value in Ect */ + uint8_t cs_pi_start_high_in_ect; + }; void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, |