diff options
| author | Scott Chao <Scott_Chao@wistron.com> | 2023-02-21 11:34:35 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-04 02:05:05 +0000 |
| commit | 40e1cce7e1b62f5c4152664325776453275f6d4e (patch) | |
| tree | 71bc877908618fce9bb090b72b99e5a7a56c73d4 /src/soc/intel/alderlake/include | |
| parent | 53db677586e3e7c4a874f1ef16f34a6d01c269a0 (diff) | |
soc/intel/alderlake: Add UWES ASL into xhci.asl
Align support for enable wake-on-usb attach/detach as was
introduced in Cannon Lake in commit 811284125f0a
("soc/intel/cannonlake: Add UWES ASL into xhci.asl").
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:230398487
BRANCH=none
TEST=Verify USB-A device could wake up Moli.
Signed-off-by: Scott Chao <Scott_Chao@wistron.com>
Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/include')
| -rw-r--r-- | src/soc/intel/alderlake/include/soc/usb.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 0eb616055c..2a701c8cc2 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -163,5 +163,11 @@ struct tcss_port_config { .ocpin = (pin), \ } +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) #endif |