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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-02-12 23:01:20 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-06-14 21:16:15 +0000 |
| commit | 2fffb5df88faf6da061bd84606db8fad6453ee40 (patch) | |
| tree | 9a43a1d4e13b6f3a6b1a9094ceae3b982c6b8d29 /src/soc/intel/alderlake/chipset_pch_s.cb | |
| parent | f9ee87ffbf6e7e5d7870bd3617c5a3368ac41c54 (diff) | |
soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder
Lake-S SKUs have GT TDC of 22A.
Based on the default settings of ADL-S FSP.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset_pch_s.cb')
0 files changed, 0 insertions, 0 deletions