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| author | Usha P <usha.p@intel.com> | 2021-11-15 18:40:00 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-29 09:46:40 +0000 |
| commit | 5b94cd9e9d0aae0bfba68fa65bf94a0d5985fa87 (patch) | |
| tree | f5f320155db2cb55c5ffad610ab693de9d5fe790 /src/soc/intel/alderlake/bootblock | |
| parent | 248dbe0908f1b934d465550987a2497cd6593b4b (diff) | |
soc/intel/common: Include Alder Lake-N device IDs
Add Alder Lake-N specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.
Document Number: 619501, 645548
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0974fc6ee2ca41d9525cc83155772f111c1fdf86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/bootblock')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2fc8eab79c..76e6c804c2 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -27,6 +27,7 @@ static struct { { CPUID_ALDERLAKE_A1, "Alderlake Platform" }, { CPUID_ALDERLAKE_A2, "Alderlake Platform" }, { CPUID_ALDERLAKE_A3, "Alderlake Platform" }, + { CPUID_ALDERLAKE_N_A0, "Alderlake-N Platform" }, }; static struct { @@ -43,6 +44,8 @@ static struct { { PCI_DEVICE_ID_INTEL_ADL_P_ID_9, "Alderlake-P" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_1, "Alderlake-M" }, { PCI_DEVICE_ID_INTEL_ADL_M_ID_2, "Alderlake-M" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_1, "Alderlake-N" }, + { PCI_DEVICE_ID_INTEL_ADL_N_ID_2, "Alderlake-N" }, }; static struct { @@ -111,6 +114,9 @@ static struct { { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT2, "Alderlake M GT2" }, { PCI_DEVICE_ID_INTEL_ADL_M_GT3, "Alderlake M GT3" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) |