diff options
| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2021-07-22 10:35:50 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-01 16:46:27 +0000 |
| commit | 9c348a7b7ea3422a74af9b820275751e9abb4a12 (patch) | |
| tree | c3fa8e32ecd2f85eb086626dc0b8fb99a76946eb /src/soc/intel/alderlake/acpi | |
| parent | 7517c39c9e815ef294197a55e3b1fa3e64543697 (diff) | |
soc/intel/alderlake: Fix processor hang while plug unplug of TBT device
Processor hang is observed while hot plug unplug of TBT device. BIOS
should execute TBT PCIe RP RTD3 flow based on the value of
TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if
BIT30 in TBT FW version is not set.
BUG=b:194880254
Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss.asl | 14 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_dma.asl | 3 |
2 files changed, 10 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index d01d872e5e..82cbad63a8 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -555,12 +555,13 @@ Scope (\_SB.PCI0) Printf("TDM0 does not exist.") } Else { If (\_SB.PCI0.TDM0.STAT == 1) { - If (\_SB.PCI0.TDM0.INFR != 1) { - Return - } /* DMA0 is not in D3Cold now. */ \_SB.PCI0.TDM0.D3CE() /* Enable DMA RTD3 */ + If (\_SB.PCI0.TDM0.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) { /* Put RP0 to D3 cold. */ @@ -613,12 +614,13 @@ Scope (\_SB.PCI0) Printf("TDM1 does not exist.") } Else { If (\_SB.PCI0.TDM1.STAT == 1) { - If (\_SB.PCI0.TDM1.INFR != 1) { - Return - } /* DMA1 is not in D3Cold now */ \_SB.PCI0.TDM1.D3CE() /* Enable DMA RTD3. */ + If (\_SB.PCI0.TDM1.IF30 != 1) { + Return + } + Printf("Push TBT RPs to D3Cold together") If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) { /* Put RP2 to D3 cold. */ diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index d00f79432d..0b5e03f913 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve) , 6, PMES, 1, /* 15, PME_STATUS */ Offset(0xC8), /* 0xC8, TBT NVM FW Revision */ - , 31, + , 30, + IF30, 1, /* ITBT FW Version Bit30 */ INFR, 1, /* TBT NVM FW Ready */ Offset(0xEC), /* 0xEC, TBT TO PCIE Register */ TB2P, 32, /* TBT to PCIe */ |