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authorSean Rhodes <sean@starlabs.systems>2023-02-27 13:08:50 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-03-01 14:25:38 +0000
commitfd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4 (patch)
tree33da5d54d2281c707500049e86cabfff7e4d5077 /src/soc/intel/alderlake/acpi/tcss_xhci.asl
parentfd51af6286d939a8308ff65260f0fa7ac948507d (diff)
soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi/tcss_xhci.asl')
-rw-r--r--src/soc/intel/alderlake/acpi/tcss_xhci.asl8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
index c0dc141530..ddc5a6665d 100644
--- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl
+++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl
@@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized)
Method (_S0W, 0x0, NotSerialized)
{
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Return (0x4)
#else
Return (0x3)
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
}
/*
@@ -43,7 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
*/
Name (SD3C, 0)
-#if !CONFIG(SOC_INTEL_ALDERLAKE_S3)
+#if CONFIG(D3COLD_SUPPORT)
Method (_PR0)
{
Return (Package () { \_SB.PCI0.D3C })
@@ -53,7 +53,7 @@ Method (_PR3)
{
Return (Package () { \_SB.PCI0.D3C })
}
-#endif // SOC_INTEL_ALDERLAKE_S3
+#endif // D3COLD_SUPPORT
/*
* XHCI controller _DSM method