diff options
| author | Dinesh Gehlot <digehlot@google.com> | 2023-02-24 05:09:04 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-02-24 12:08:33 +0000 |
| commit | 930fded5b7f50333179c71e0d1fcf1857862dfe0 (patch) | |
| tree | f109fdce1255d939d70a4f095bd4f5a61fbf04c7 /src/soc/intel/alderlake/Makefile.inc | |
| parent | 9a5b743e56432ff13cecc814f1127f382779432d (diff) | |
soc/intel/adl: Select CSE defined ME spec version for alderlake
Alderlake based SoCs uses Intel's Management Engine (ME), version 16.
This patch selects ME 16 specification defined at common code and
removes alderlake SoC specific ME code and data structures.
BUG=b:260309647
Test=Build verified for brya.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/alderlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index fa52efbc6f..943b158564 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -33,7 +33,6 @@ ramstage-y += fsp_params.c ramstage-y += graphics.c ramstage-y += hsphy.c ramstage-y += lockdown.c -ramstage-y += me.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c ramstage-y += pmc.c |