diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-29 21:32:54 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-23 08:59:50 +0000 |
| commit | 95be012c11936676f6573880d5fd01826ae6f9fe (patch) | |
| tree | 6ca992dc8602b24a402d4c6c2d40f5d6ee152281 /src/soc/intel/alderlake/Kconfig | |
| parent | 558d8b79e6b898e0f63772993f578aa4dd42128b (diff) | |
soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0e5a671be2..664876a003 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -527,4 +527,30 @@ config FSP_PUBLISH_MBP_HOB later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. +config INCLUDE_HSPHY_IN_FMAP + bool "Include PCIe 5.0 HSPHY firmware in flash" + default n + help + Set this option to cache the PCIe 5.0 HSPHY firmware after it is + fetched from ME during boot. By default coreboot will fetch the + HSPHY FW from ME, but if for some reason ME is not enabled or + visible, the cached blob will be attempted to initialize the PCIe + 5.0 root port. Select it if ME is soft disabled or disabled with HAP + bit. If possible, the HSPHY FW will be saved to flashmap region if + the firmware file is not provided directly in the HSPHY_FW_FILE + Kconfig. + +config HSPHY_FW_FILE + string "HSPHY firmware file path" + depends on INCLUDE_HSPHY_IN_FMAP + help + Path pointing to the PCIe 5.0 HSPHY file. The file can be extracted + from full firmware image or ME region using UEFITool. If left empty, + HSPHY loading procedure will try to save the firmware to the flashmap + region if fetched successfully from ME. + +config HSPHY_FW_MAX_SIZE + hex + default 0x8000 + endif |