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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-10-16 14:48:46 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:48:13 +0000 |
| commit | 543e01a29c01b634d61f3dee669f0ac44b7550a5 (patch) | |
| tree | 5161bf98230226e0b4bcd0768654779a0d9e19e5 /src/soc/imgtec/pistachio/spi.c | |
| parent | ff4f80bc4ba035fb042653a1fa14c1b5ef9b1f30 (diff) | |
amd/stoneyridge/include/soc: Re-arrange NB IOAPIC definitions
There's no indication that they are accessed through D0F0. Add a D0F0 header
and move IOAPIC definitions under it. The registers defined to be accessed
through index/data pair should be indented relative to the index/data pair
definition.
BUG=b:117754786
TEST=Build grunt.
Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29155
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/spi.c')
0 files changed, 0 insertions, 0 deletions