drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M

Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM.  This split occurs because ESRAM is too
small to hold everything while debugging.

Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15848
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

0 files changed, 0 insertions, 0 deletions