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authorUwe Poeche <uwe.poeche@siemens.com>2022-03-28 12:39:01 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-18 11:14:09 +0000
commit539fd2ac5a0f510d8434d4cc8a597f092325b8c8 (patch)
tree26b7b42ba97288d14ff218c4b49d2fc741a22d21 /src/soc/cavium/common
parentdb9873b69c52cc1eac5bfef72228f071e303a78f (diff)
intel/common/block: Provide RAPL and min clock ratio switches in common
There are two APL specific config switches for RAPL and min. cpu clock (APL_SKIP_SET_POWER_LIMITS, APL_SET_MIN_CLOCK_RATIO). These switches could be used in future in other CPU platforms. Move them to common code instead of having them just for one SOC. Test: Make sure that the clock ratio (MSR 0x198) and the RAPL settings (MSR0x610) do not change with this patch applied on mc_apl{1,4,5} mainboard. Change-Id: I3d63d1b9b6c96586a3c20bf8c1d8001b1d7c4bed Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/cavium/common')
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