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| author | Zheng Bao <fishbaozi@gmail.com> | 2022-02-15 00:38:54 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 17:14:35 +0000 |
| commit | b09166d0e62ba8ebe0c27bb7b1e20cac4885aa08 (patch) | |
| tree | cd84fb70aa23aed2dae82431e474d29e0ee59743 /src/soc/cavium/cn81xx/mmu.c | |
| parent | 6c5efcd26856aef56dd88c231b6e9dc453e80f71 (diff) | |
mb/google/guybrush: Add a mainboard specific SPL table
Chromebook needs to do some additional check, which is not
available in the AMD's PI released SPL table.
BUG=b:216096562
Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/cavium/cn81xx/mmu.c')
0 files changed, 0 insertions, 0 deletions