cavium: Add CN81xx SoC and eval board support

This adds Cavium CN81xx SoC and SFF EVB files.

Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK

BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs

romstage:
- Use minimal DRAM init only

devicetree:
- Convert FTD to static C file containing key value pairs

Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)

Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init

Not working:
- Booting a payload
- Booting upstream ATF

TODO:
- Configuration straps

Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

11 files changed, 432 insertions, 0 deletions

diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
new file mode 100644
index 0000000000..e23549450b
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__
+#define __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__
+
+#define MAX_DRAM_ADDRESS	0x2000000000ULL	/* 128GB */
+
+/* Physical addressed with bit 47 set indicate I/O memory space. */
+
+/* ARM code entry vector */
+#define BOOTROM_OFFSET		0x100000
+
+/* L2C */
+#define L2C_PF_BAR0		0x87E080800000ULL
+#define L2C_TAD0_PF_BAR0	(0x87E050000000ULL + 0x10000)
+#define L2C_TAD0_INT_W1C	(0x87E050000000ULL + 0x40000)
+#define L2C_CBC0_PF_BAR0	0x87E058000000ULL
+#define L2C_MCI0_PF_BAR0	0x87E05C000000ULL
+
+/* LMC */
+#define LMC0_PF_BAR0		0x87E088000000ULL
+#define LMC0_DDR_PLL_CTL0 	0x258
+
+/* OCLA */
+
+/* IOB */
+#define IOBN0_PF_BAR0		0x87E0F0000000ULL
+#define MRML_PF_BAR0		0x87E0FC000000ULL
+
+/* SMMU */
+#define SMMU_PF_BAR0		0x830000000000ULL
+
+/* GTI */
+#define GTI_PF_BAR0		0x844000000000ULL
+
+/* PCC */
+#define ECAM_PF_BAR2		0x848000000000ULL
+
+/* CPT */
+/* SLI */
+
+/* RST */
+#define RST_PF_BAR0		(0x87E006000000ULL + 0x1600)
+#define FUSF_PF_BAR0		0x87E004000000ULL
+#define MIO_FUS_PF_BAR0		0x87E003000000ULL
+#define MIO_BOOT_PF_BAR0	0x87E000000000ULL
+
+/* PTP */
+#define MIO_PTP_PF_BAR0		0x807000000000ULL
+
+/* GIC */
+/* NIC */
+/* LBK */
+
+#define GTI_PF_BAR0		0x844000000000ULL
+
+/* DAP */
+/* BCH */
+/* KEY */
+/* RNG */
+
+#define GSER0_PF_BAR0		(0x87E090000000ULL + (0 << 24))
+#define GSER1_PF_BAR0		(0x87E090000000ULL + (1 << 24))
+#define GSER2_PF_BAR0		(0x87E090000000ULL + (2 << 24))
+#define GSER3_PF_BAR0		(0x87E090000000ULL + (3 << 24))
+#define GSERx_PF_BAR0(x) \
+	((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \
+	 (0x87E090000000ULL + ((x) << 24)) : 0)
+
+/* PEM */
+/* SATA */
+/* USB */
+
+/* UAA */
+#define UAA0_PF_BAR0		(0x87E028000000ULL + (0 << 24))
+#define UAA1_PF_BAR0		(0x87E028000000ULL + (1 << 24))
+#define UAA2_PF_BAR0		(0x87E028000000ULL + (2 << 24))
+#define UAA3_PF_BAR0		(0x87E028000000ULL + (3 << 24))
+#define UAAx_PF_BAR0(x) \
+	((((x) == 0) || ((x) == 1) || ((x) == 2) || ((x) == 3)) ? \
+	 (0x87E028000000ULL + ((x) << 24)) : 0)
+
+
+/* TWSI */
+#define MIO_TWS0_PF_BAR0	(0x87E0D0000000ULL + (0 << 24))
+#define MIO_TWS1_PF_BAR0	(0x87E0D0000000ULL + (1 << 24))
+#define MIO_TWSx_PF_BAR0(x) \
+	((((x) == 0) || ((x) == 1)) ? (0x87E0D0000000ULL + ((x) << 24)) : 0)
+
+/* GPIO */
+#define GPIO_PF_BAR0		0x803000000000ULL
+
+/* SGPIO */
+#define SGP_PF_BAR0		0x803000000000ULL
+
+/* SMI */
+
+/* SPI */
+#define MPI_PF_BAR0		(0x804000000000ULL + 0x1000)
+
+/* PCM */
+/* PBUS */
+/* NDF */
+/* EMM */
+
+/* VRM */
+/* VRM BARs are spaced apart by 0x1000000 */
+#define VRM0_PF_BAR0		0x87E021000000ULL
+
+#endif /* __SOC_CAVIUM_CN81XX_ADDRESSMAP_H__ */
diff --git a/src/soc/cavium/cn81xx/include/soc/clock.h b/src/soc/cavium/cn81xx/include/soc/clock.h
new file mode 100644
index 0000000000..d436c121cb
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/clock.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ * Copyright 2003-2017  Cavium Inc.  <support@cavium.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_
+#define SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_
+
+#include <types.h>
+
+u64 thunderx_get_ref_clock(void);
+u64 thunderx_get_io_clock(void);
+u64 thunderx_get_core_clock(void);
+
+#endif /* SRC_SOC_CAVIUM_CN81XX_INCLUDE_CLOCK_H_ */
diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h
new file mode 100644
index 0000000000..df3c06955a
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/cpu.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ * Copyright 2003-2017    Cavium Inc.  <support@cavium.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_CPU_H__
+#define __SOC_CAVIUM_CN81XX_CPU_H__
+
+size_t cpu_get_num_cores(void);
+
+#endif	/* __SOC_CAVIUM_CN81XX_CPU_H__ */
diff --git a/src/soc/cavium/cn81xx/include/soc/gpio.h b/src/soc/cavium/cn81xx/include/soc/gpio.h
new file mode 100644
index 0000000000..6986482f79
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/gpio.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_GPIO_H
+#define __COREBOOT_SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_GPIO_H
+
+#include <types.h>
+
+typedef u32 gpio_t;
+#include <gpio.h>
+
+/* The following functions must be implemented by SoC/board code. */
+
+
+gpio_t gpio_pin_count(void);
+void gpio_invert(gpio_t gpio, int value);
+int gpio_strap_value(gpio_t gpio);
+
+void gpio_init(void);
+
+#endif
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
new file mode 100644
index 0000000000..f0ac2c9da5
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <soc/addressmap.h>
+#include <arch/header.ld>
+
+SECTIONS
+{
+	DRAM_START(0x00000000)
+	/* FIXME: Place BL31 in first 1MiB */
+
+	/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
+	SRAM_START(BOOTROM_OFFSET)
+	STACK(BOOTROM_OFFSET, 16K)
+	TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)
+	PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)
+	PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
+
+	BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+	ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
+	SRAM_END(BOOTROM_OFFSET + 0x80000)
+	TTB(BOOTROM_OFFSET + 0x80000, 128K)
+	RAMSTAGE(BOOTROM_OFFSET + 0xa0000, 512K)
+
+	/* Leave some space for the payload */
+	POSTRAM_CBFS_CACHE(0x2000000, 16M)
+}
diff --git a/src/soc/cavium/cn81xx/include/soc/sdram.h b/src/soc/cavium/cn81xx/include/soc/sdram.h
new file mode 100644
index 0000000000..5a3e5196b5
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/sdram.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ * Copyright 2003-2017    Cavium Inc.  <support@cavium.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_SDRAM_H__
+#define __SOC_CAVIUM_CN81XX_SDRAM_H__
+
+#include <types.h>
+
+size_t sdram_size_mb(void);
+void sdram_init(void);
+
+#endif	/* !__SOC_CAVIUM_CN81XX_SDRAM_H__ */
diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h
new file mode 100644
index 0000000000..a751e64846
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/soc.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
+#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
+
+#include <inttypes.h>
+#include <types.h>
+
+/* MIO BOOT Registers */
+struct cn81xx_mio_boot {
+	u8 rsvd0[0xb0];
+	u64 thr;
+	u8 rsvd1[0x8];
+	u64 pin_defs;
+	u8 rsvd2[0x8];
+	u64 ap_jump;
+	u64 rom_limit;
+	u8 rsvd3[0x18];
+	u64 bist_stat;
+};
+check_member(cn81xx_mio_boot, bist_stat, 0xf8);
+
+/*
+ * 0 = Board supplies 100MHz to DLM_REF_CLK
+ * 1 = bOard supplies 50MHz to PLL_REFCLK
+ * */
+#define MIO_BOOT_PIN_DEFS_UART0_RTS	(1 << 16)
+#define MIO_BOOT_PIN_DEFS_UART1_RTS	(1 << 17)
+
+#endif  /* ! __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H */
diff --git a/src/soc/cavium/cn81xx/include/soc/spi.h b/src/soc/cavium/cn81xx/include/soc/spi.h
new file mode 100644
index 0000000000..bb69daac91
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/spi.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COREBOOT_SRC_SOC_CN81XX_INCLUDE_SOC_SPI_H
+#define __COREBOOT_SRC_SOC_CN81XX_INCLUDE_SOC_SPI_H
+
+/* This driver serves as a CBFS media source. */
+#include <spi-generic.h>
+#include <stddef.h>
+
+void spi_enable(const size_t bus);
+void spi_disable(const size_t bus);
+void spi_set_cs(const size_t bus,
+		const size_t chip_select,
+		const size_t assert_is_low);
+void spi_set_clock(const size_t bus,
+		   const size_t speed_hz,
+		   const size_t idle_low,
+		   const size_t idle_cycles);
+void spi_set_lsbmsb(const size_t bus, const size_t lsb_first);
+void spi_init_custom(const size_t bus,
+		     const size_t speed_hz,
+		     const size_t idle_low,
+		     const size_t idle_cycles,
+		     const size_t lsb_first,
+		     const size_t chip_select,
+		     const size_t assert_is_low);
+#endif  /* ! __COREBOOT_SRC_SOC_CN81XX_INCLUDE_SOC_SPI_H */
diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h
new file mode 100644
index 0000000000..a12f68e422
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/timer.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_TIMER_H__
+#define __SOC_CAVIUM_CN81XX_TIMER_H__
+
+#include <inttypes.h>
+#include <types.h>
+#include <timer.h>
+#include <delay.h>
+
+/* Watchdog functions */
+void watchdog_set(const size_t index, unsigned int timeout_ms);
+void watchdog_poke(const size_t index);
+void watchdog_disable(const size_t index);
+int watchdog_is_running(const size_t index);
+
+#endif	/* __SOC_CAVIUM_CN81XX_TIMER_H__ */
diff --git a/src/soc/cavium/cn81xx/include/soc/twsi.h b/src/soc/cavium/cn81xx/include/soc/twsi.h
new file mode 100644
index 0000000000..6c5211e63b
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/twsi.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <types.h>
+#include <device/i2c.h>
+
+#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H
+#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_TWSI_H
+
+int twsi_init(unsigned int bus, enum i2c_speed hz);
+
+#endif
diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h
new file mode 100644
index 0000000000..e4022068bc
--- /dev/null
+++ b/src/soc/cavium/cn81xx/include/soc/uart.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H
+#define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H
+
+#include <inttypes.h>
+#include <types.h>
+
+int uart_is_enabled(const size_t bus);
+int uart_setup(const size_t bus, int baudrate);
+
+#endif	/* __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H */