diff options
| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2018-08-10 16:07:23 -0700 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-08-24 12:29:28 +0000 |
| commit | 31a4700ce9fbd1a4a04e88198e18d50cd9a81897 (patch) | |
| tree | eb6f616c3f96a1b9bdc3be782c6cb5d6b920b6b7 /src/soc/cavium/cn81xx/include | |
| parent | 70866e9f383f4a2bb895486616136ba46add5bfa (diff) | |
soc/cn81xx: Add vboot support
* Add VERSTAGE and VBOOT_WORK to memlayout.
* Add hard and soft reset.
* Add missing makefile and kconfig includes.
Change-Id: I0d7e3c220f5c2c50c4ffe59ac929cb865bfac0ad
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/include')
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/memlayout.ld | 6 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index f6983064fc..f188961930 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -62,6 +62,7 @@ /* RST */ #define RST_PF_BAR0 (0x87E006000000ULL + 0x1600) +#define RST_SOFT_RESET (RST_PF_BAR0 + 0x80ULL) #define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL) #define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL) #define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL) diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index b80d152f97..e3bf61f1f4 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -28,14 +28,18 @@ SECTIONS /* Insecure region 1MiB - TOP OF DRAM */ /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ SRAM_START(BOOTROM_OFFSET) + STACK(BOOTROM_OFFSET, 16K) TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) + VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) + SRAM_END(BOOTROM_OFFSET + 0x80000) + TTB(BOOTROM_OFFSET + 0x80000, 512K) RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) /* Stack for secondary CPUs */ |