diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-03-26 15:54:41 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-10 07:03:29 +0000 |
| commit | 06c7d64be9fa0355ed7cfc092db93963a254295a (patch) | |
| tree | 3082efb85b5e6b0f3c67be16818524039fdea84e /src/soc/cavium/cn81xx/include | |
| parent | 8cbd569f74d8929387730e45b0d6e993b1365c02 (diff) | |
soc/cavium: Enable MMU
* Configure and enable MMU.
* Cover the whole I/O space.
* A minimum of 512KB TTB space is required.
* Use secure mem attribute as firmware is running in ARM TZ region.
Tested on Cavium SoC.
Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/include')
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/addressmap.h | 4 | ||||
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/memlayout.ld | 4 | ||||
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/mmu.h | 21 |
3 files changed, 27 insertions, 2 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h index e23549450b..8c993ad9d2 100644 --- a/src/soc/cavium/cn81xx/include/soc/addressmap.h +++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h @@ -23,6 +23,10 @@ /* ARM code entry vector */ #define BOOTROM_OFFSET 0x100000 +/* Start of IO space */ +#define IO_SPACE_START 0x800000000000ULL +#define IO_SPACE_SIZE 0x100000000000ULL + /* L2C */ #define L2C_PF_BAR0 0x87E080800000ULL #define L2C_TAD0_PF_BAR0 (0x87E050000000ULL + 0x10000) diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index f0ac2c9da5..d7ee5766a0 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -33,8 +33,8 @@ SECTIONS BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) SRAM_END(BOOTROM_OFFSET + 0x80000) - TTB(BOOTROM_OFFSET + 0x80000, 128K) - RAMSTAGE(BOOTROM_OFFSET + 0xa0000, 512K) + TTB(BOOTROM_OFFSET + 0x80000, 512K) + RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) /* Leave some space for the payload */ POSTRAM_CBFS_CACHE(0x2000000, 16M) diff --git a/src/soc/cavium/cn81xx/include/soc/mmu.h b/src/soc/cavium/cn81xx/include/soc/mmu.h new file mode 100644 index 0000000000..9b811c3966 --- /dev/null +++ b/src/soc/cavium/cn81xx/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H +#define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H + +void soc_mmu_init(void); + +#endif /* ! __SOC_CAVIUM_CN81XX_INCLUDE_SOC_MMU_H */ |