soc/cavium: Add secondary CPU support

Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

3 files changed, 62 insertions, 1 deletions

diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
index 8c993ad9d2..938dd3233d 100644
--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -58,9 +58,14 @@
 
 /* RST */
 #define RST_PF_BAR0		(0x87E006000000ULL + 0x1600)
+#define RST_PP_AVAILABLE	(RST_PF_BAR0 + 0x138ULL)
+#define RST_PP_RESET		(RST_PF_BAR0 + 0x140ULL)
+#define RST_PP_PENDING		(RST_PF_BAR0 + 0x148ULL)
+
 #define FUSF_PF_BAR0		0x87E004000000ULL
 #define MIO_FUS_PF_BAR0		0x87E003000000ULL
 #define MIO_BOOT_PF_BAR0	0x87E000000000ULL
+#define MIO_BOOT_AP_JUMP	(MIO_BOOT_PF_BAR0 + 0xD0ULL)
 
 /* PTP */
 #define MIO_PTP_PF_BAR0		0x807000000000ULL
diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h
index df3c06955a..b2472d78e3 100644
--- a/src/soc/cavium/cn81xx/include/soc/cpu.h
+++ b/src/soc/cavium/cn81xx/include/soc/cpu.h
@@ -17,6 +17,59 @@
 #ifndef __SOC_CAVIUM_CN81XX_CPU_H__
 #define __SOC_CAVIUM_CN81XX_CPU_H__
 
-size_t cpu_get_num_cores(void);
+/**
+ * Number of the Core on which the program is currently running.
+ *
+ * @return Number of cores
+ */
+size_t cpu_self_get_core_id(void);
+
+/**
+ * Return a mask representing this core in a 64bit bitmask
+ *
+ * @return The mask of active core.
+ */
+uint64_t cpu_self_get_core_mask(void);
+
+/**
+ * Return the mask of available cores.
+ *
+ * @return Mask of available cores
+ */
+uint64_t cpu_get_available_core_mask(void);
+
+/**
+ * Return the number of cores available in the chip.
+ *
+ * @return The number of available cores.
+ */
+size_t cpu_get_num_available_cores(void);
+
+/**
+ * Init secondary core and call the provided entry for given core.
+ * A stack of size CONFIG_STACK_SIZE is set up for each core in REGION
+ * stack_sec. The unique core id is passed to the entry point functions.
+ *
+ * @return zero on success
+ */
+size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id));
+
+/**
+ * Secondary ASM CPU entry point.
+ * For internal use only.
+ */
+void secondary_init(void);
+
+/**
+ * Secondary CPU C entry point.
+ * For internal use only.
+ */
+void secondary_cpu_init(size_t core_id);
+
+/* Symbols in memlayout.ld */
+
+extern u8 _stack_sec[];
+extern u8 _estack_sec[];
+#define _stack_sec_size (_estack_sec - _stack_sec)
 
 #endif	/* __SOC_CAVIUM_CN81XX_CPU_H__ */
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index d7ee5766a0..0400d2985e 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -35,6 +35,9 @@ SECTIONS
 	SRAM_END(BOOTROM_OFFSET + 0x80000)
 	TTB(BOOTROM_OFFSET + 0x80000, 512K)
 	RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
+	/* Stack for secondary CPUs */
+	REGION(stack_sec, BOOTROM_OFFSET + 0x180000,
+	       CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000)
 
 	/* Leave some space for the payload */
 	POSTRAM_CBFS_CACHE(0x2000000, 16M)